1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a regular layout region.
2. Description of Related Art
As basic structures of SRAM (Static Random Access Memory) memory cells for use in semiconductor memory devices, there are known a high-resistance load type SRAM including four MOS (Metal Oxide Semiconductor) transistors (two drive MOS transistors and two transfer MOS transistors) and two high-resistance elements, and a CMOS (Complementary Metal Oxide Semiconductor) type SRAM including six MOS transistors (two drive MOS transistors, two load MOS transistors, and two transfer MOS transistors) (e.g., see U.S. Pat. Nos. 5,930,163, 6,900,513, 6,597,041, and 6,922,354). Along with the recent tendency toward the reduction in voltage due to the miniaturization of design rules, CMOS-type SRAMs are widely employed as semiconductor memory devices which are mixed in a logic IC (Integrated Circuit), in view of operating characteristics.
FIG. 30 shows a layout example of a lower conductive layer of a memory cell of a CMOS-type SRAM disclosed in U.S. Pat. No. 5,930,163. The memory cell disclosed in U.S. Pat. No. 5,930,163 includes p-wells and n-wells which are alternately formed in the lateral direction of FIG. 30. N-channel MOS transistors N1 to N4 are formed on the p-wells, and p-channel MOS transistors P1 and P2 are formed on the n-wells. In gate electrode interconnect layers 7 and active regions 6 of the MOS transistors, a large number of M1-connection plugs 10 such as contact holes or via holes are formed so as to be connected with upper-layer interconnections (not shown).
U.S. Pat. No. 6,900,513 proposes a structure capable of downsizing a memory cell. FIG. 31 is a partial sectional view showing a memory cell of a CMOS-type SRAM disclosed in U.S. Pat. No. 6,900,513. The memory cell disclosed in U.S. Pat. No. 6,900,513 includes a semiconductor substrate 2, an isolation region 5, active regions 6, gate electrode interconnect layers 7, connection plugs 10, an intermediate connection layer 20, local interconnections 26 and 27, first interconnect layers M1, a first interlayer insulating film 51, a second interlayer insulating film 52, a third interlayer insulating film 53, and a fourth interlayer insulating film 54. The connection plugs 10 which are substantially concentric with each other are disposed on and below the intermediate connection layer 20. Additionally, the local interconnection 26 connects two active regions 6 spaced from each other, and forms a capacitance with the local interconnection 27.